1. DC Load Line and Q operating point
18:10
26:38
4.3 Fixed-Bias Configuration (b) Transistor Saturation + Example 4.2
08:18
4.3 Fixed-Bias Configuration (c) Load-Line Analysis + Example 4.3
21:19
4.4 Emitter-Bias Configuration (a) Base–Emitter & Collector–Emitter Loop equations + Example 4.4
25:30
4.4 Emitter-Bias Configuration (b) Improved Bias Stability + Example 4.5
15:47
4.4 Emitter-Bias Configuration (c) Saturation Level + Example 4.6
04:24
4.4 Emitter-Bias Configuration (d) Load-Line Analysis + Example 4.7
14:41
4.5 Voltage-Divider Bias Configuration (a) Exact Analysis + Example 4.8
24:18
4.5 Voltage-Divider Bias Configuration (b) Approximate Analysis + Example 4.9
18:08
4.5 Voltage-Divider Bias Configuration (c) Example 4.10
06:26
4.6 Collector Feedback Configuration (a) Base–Emitter & Collector–Emitter Loop equations + Example 4.12
13:16
4.6 Collector Feedback Configuration (b) Example 4.13
06:04
4.6 Collector Feedback Configuration (c) Example 4.14
06:34
4.7 Emitter-Follower Configuration + Example 4.16
16:45
4.8 Common-Base Configuration + Example 4.17
13:02
3. Power Rating of Transistor + [Example 3 + Example 4 + Example 5 solutions
07:27
