Digital Design | M. Morris Mano & Michael D. Ciletti | تصميم منطقي رقمي

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تصميم منطقي رقمي – كتاب موريس مانو | Digital Design – Morris Mano & Ciletti

يرتبط المحتوى بفصول أنظمة الأعداد والبوابات المنطقية والجبر البولياني، وتبسيط الدوائر بالخرائط، والدوائر التوافقية والتتابعية، والسجلات والعدادات. تتضمن الفصول حلولًا من مسائل الكتاب.

الشرح من كتاب

Digital Design by M. Morris Mano and Michael D. Ciletti

رابط قناة اليوتويب

https://www.youtube.com/@eng.emadmahdy

لتحميل ملفات الشرح المترجمة علي جروب التليجرام للمادة

https://t.me/digital_logic_cs_si

جروب التليجرام العام لكل المواد

https://t.me/si_manual_eng

للتواصل واتساب

https://wa.me/201271482006

محتوي الكورس
chapter 1: Digital Systems and Binary Numbers
1.1 Digital Systems
1.2 Binary Numbers
1.3 Number‐Base Conversions
1.4 Octal and Hexadecimal Numbers
1.5 Complements of Numbers
1.6 Signed Binary Numbers
1.7 Binary Codes
1.8 Binary Storage and Registers
1.9 Binary Logic chapter
2: Boolean Algebra and Logic Gates
2.1 Introduction
2.2 Basic Definitions
2.3 Axiomatic Definition of Boolean Algebra
2.4 Basic Theorems and Properties of Boolean Algebra
2.5 Boolean Functions
2.6 Canonical and Standard Forms
2.7 Other Logic Operations
2.8 Digital Logic Gates
2.9 Integrated Circuits chapter
3: Gate-Level Minimization
3.1 Introduction
3.2 The Map Method
3.3 Four‐Variable K-Map
3.4 Product‐of‐Sums Simplification
3.5 Don’t‐Care Conditions
3.6 NAND and NOR Implementation
3.7 Other Two‐Level Implementations
3.8 Exclusive‐OR Function
chapter 4: Combinational Logic
4.1 Introduction
4.2 Combinational Circuits
4.3 Analysis Procedure
4.4 Design Procedure
4.5 Binary Adder–Subtractor
4.6 Decimal Adder
4.7 Binary Multiplier
4.8 Magnitude Comparator
4.9 Decoders
4.10 Encoders
4.11 Multiplexers
chapter 5: Synchronous Sequential Logic
5.1 Introduction
5.2 Sequential Circuits
5.3 Storage Elements: Latches
5.4 Storage Elements: Flip‐Flops
5.5 Analysis of Clocked Sequential Circuits
5.6 Synthesizable HDL Models of Sequential Circuits
5.7 State Reduction and Assignment
5.8 Design Procedure chapter
6: Registers and Counters
6.1 Registers
6.2 Shift Registers
6.3 Ripple Counters
6.4 Synchronous Counters
6.5 Other Counters chapter
7: Memory and Programmable Logic
7.1 Introduction
7.2 Random‐Access Memory
7.3 Memory Decoding

7.4 Error Detection and Correction
7.5 Read‐Only Memory
7.6 Programmable Logic Array
7.7 Programmable Array Logic
7.8 Sequential Programmable Devices

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Course Content

CHAPTER 2 Boolean Algebra and Logic Gates

CHAPTER 2 Boolean Algebra and Logic Gates | حلول مسائل الكتاب

CHAPTER 3 Gate-Level Minimization

CHAPTER 3 Gate-Level Minimization | حلول مسائل الكتاب

CHAPTER 4 Combinational Logic

CHAPTER 4 Combinational Logic | حلول مسائل الكتاب

CHAPTER 5 Synchronous Sequential Logic

CHAPTER 5 Synchronous Sequential Logic | حلول مسائل الكتاب

CHAPTER 6 Registers and Counters

CHAPTER 6 Registers and Counters | حلول مسائل الكتاب