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1. DC Load Line and Q operating point
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4.3 Fixed-Bias Configuration (a) Base–Emitter & Collector–Emitter Loop equations + Example 4.1
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4.3 Fixed-Bias Configuration (b) Transistor Saturation + Example 4.2
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4.3 Fixed-Bias Configuration (c) Load-Line Analysis + Example 4.3
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4.4 Emitter-Bias Configuration (a) Base–Emitter & Collector–Emitter Loop equations + Example 4.4
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4.4 Emitter-Bias Configuration (b) Improved Bias Stability + Example 4.5
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4.4 Emitter-Bias Configuration (c) Saturation Level + Example 4.6
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4.4 Emitter-Bias Configuration (d) Load-Line Analysis + Example 4.7
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4.5 Voltage-Divider Bias Configuration (a) Exact Analysis + Example 4.8
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4.5 Voltage-Divider Bias Configuration (b) Approximate Analysis + Example 4.9
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4.5 Voltage-Divider Bias Configuration (c) Example 4.10
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4.6 Collector Feedback Configuration (a) Base–Emitter & Collector–Emitter Loop equations + Example 4.12
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4.6 Collector Feedback Configuration (b) Example 4.13
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4.6 Collector Feedback Configuration (c) Example 4.14
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4.7 Emitter-Follower Configuration + Example 4.16
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4.8 Common-Base Configuration + Example 4.17
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3. Power Rating of Transistor + [Example 3 + Example 4 + Example 5 solutions
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