Computer Architecture | معمارية حاسب | هندسة و علوم حاسب

محتوى الدورة

Chapter 1 Register Transfer & Microoperation

1. Register Transfer Language

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2. Register Transfer part 1

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3. Register Transfer part 2

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4. Connecting Registers

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5. Bus and Bus Transfer

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تمرين مهم Midterm 2024 Exam Spring 2024 – (44-45H) Dr Hesham Question 2 (bus system using MUX and Decoder )

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6. Memory Transfer

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7. Microoperations

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8. Arithmetic Circuit

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9. Full Arithmetic Circuit

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10. Logic Microoperations

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11. Application of Logic Microoperations

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12. Shift Microoperation

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13. Hardware Implementation Shift Microoperation

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14. Arithmetic Logic Shift Unit

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ملخص قوانين الشابتر pdf

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chapter 1 تجميعات علي

تجميعات علي شابتر 1 من الفاينال

Chapter 2 Basic Computer Organization and Design

2.1 Instruction Codes – a) The Basic Computer

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2.1 Instruction Codes – b) Instruction Format and Addressing Modes

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2.2 Computer Registers – a) Basic Computer Registers

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2.2 Computer Registers – b) Basic Computer Common Bus System

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2.3 Basic Computer instructions

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2.4 Timing and Control

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2-5 part 1 Instruction Cycle

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2-5 part 2 Register Reference Instructions

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2.6 Memory Reference instructions

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2.7 Input-Output and Interrupt

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2.8 Complete Computer Description

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2.9 Design of Basic Computer

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2.10 part 1 Design of Accumulator Logic

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ملخص قوانين الشابتر pdf

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chapter 2 تجميعات علي

Chapter 3 Programming The Basic Computer

chapter 3 تجميعات علي

Midterm 2022 first term [Dr Ahmed AL-Ghamdi]

Midterm 2022 second term [Dr Ahmed AL-Ghamdi]

Midterm 2024 Exam Spring 2024 – (44-45H) Dr Heham (الاختبار علي أول 3 شباتر)

Midterm Exam, Spring 2023, 44-45 Dr Hatem

Midterm 2025, second term 1446 H [Dr Mohamed Abdelaziz]

Chapter 4 Central Processing Unit

4.1 Introduction

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4.2 General Register Organization

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4.3 Stack Organization (a) Register Stack

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4.3 Stack Organization (b) Memory stack

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4.3 Stack Organization (c) Reverse Polish Notation

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4.4 Instruction Formats (a) Processor Organization

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4.4 Instruction Formats (b) Three, Two, One, Zero Address Instructions

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4.5 Addressing Modes

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4.6 Data Transfer and Manipulation

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4.7 Program Control

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ملخص قوانين الشابتر pdf

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Chapter 5 Memory Organization

Chapter 6 CISC vs RISC

Chapter 7 Pipelining

Chapter 8 Parallel Computer Architecture

Chapter 4 book solution [ واجب د هشام + د شيماء الأول ]

Q4.1 solution

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Q4.2 solution

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Q4.3 solution

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Q4.5 solution

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Q4.6 solution

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Q4.7 solution

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Q4.12 solution

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Q4.15 solution

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Q4.18 solution

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Q4.19 solution

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Q4.20 solution

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Q4.21 solution

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Q4.22 solution

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Q4.23 solution

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Chapter 5 book solution [ واجب د هشام + د شيماء الثاني ]

Problem 5.1 solution book

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Problem 5.2 solution book

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Problem 5.3 solution book

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Problem 5.4 solution book

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Problem 5.5 solution book

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Problem 5.6 solution book

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Problem 5.7 solution book

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Problem 5.10 solution book

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Problem 5.11 solution book

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Problem 5.12 solution book

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Problem 5.16 solution book

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Problem 5.17 solution book

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Chapter 6 book solution [ واجب د هشام + د شيماء الثالث ]

Chapter 8 book solution [ واجب د هشام + د شيماء الرابع ]

Problem 8.1 solution book

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Problem 8.3 solution book

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Problem 8.4 solution book

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Problem 8.7-(a) solution book

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Problem 8.7-(b) solution book

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Problem 8.7-(c) solution book

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Problem 8.7-(d) solution book

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Problem 8.8 solution book

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Problem 8.9 solution book

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Assignment 1 solution Dr Karim Sedawy

Assignment (1) – Q1

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Assignment (1) – Q2

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Assignment (1) – Q3

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Assignment (1) – Q4

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Assignment (1) – Q5

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Assignment (1) – Q6

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Assignment (1) – Q7

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Assignment (1) – Q8

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Assignment (1) – Q9

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تحميل ملف الحل pdf

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Assignment 2 solution Dr Karim Sedawy

Assignment 3 solution Dr Karim Sedawy

Assignment 5 solution Dr Karim Sedawy

Assignment 1 solution Dr Ahmed Mahfouz

Question 1 solution

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Question 2 solution

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Question 3 solution

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Question 4 solution

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Question 5 solution

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Question 6 solution

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Question 7 solution

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Question 8 solution

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Question 9 solution

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Question 10 solution

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Question 11 solution

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تحميل حل الواجب كامل pdf

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[Assignment 1 solution [Dr Mohamed Abd El Aziz + Dr Ahmed El Ghamdi

Assignment (1) – Q1

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Assignment (1) – Q2

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Assignment (1) – Q3

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Assignment (1) – Q4

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Assignment (1) – Q5

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Assignment (1) – Q6

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Assignment (1) – Q7

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Assignment (1) – Q8

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Assignment (1) – Q9

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Assignment (1) – Q10

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Assignment (1) – Q11

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Assignment (1) – Q12

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Assignment (1) – Q13

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تحميل ملف الحل pdf

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[Assignment 2 solution [Dr Mohamed Abd El Aziz + Dr Ahmed El Ghamdi

Assignment (2) – Q1 (Problem 5.1 book)

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Assignment (2) – Q2 (Problem 5.2 book)

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Assignment (2) – Q3 (Problem 5.3 book)

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Assignment (2) – Q4 (Problem 5.4 book)

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Assignment (2) – Q5 (Problem 5.5 book)

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Assignment (2) – Q6 (Problem 5.6 book)

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Assignment (2) – Q7 (Problem 5.9 book)

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Assignment (2) – Q8 (Problem 5.10 book)

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Assignment (2) – Q9

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Assignment (2) – Q10 (Problem 5.12 book)

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Assignment (2) – Q11 (Problem 5.17 book)

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Assignment (2) – Q14 (a) AR [Derive control inputs (LD, CLR, INR)]

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Assignment (2) – Q14 (b) DR [Derive control inputs (LD, CLR, INR)]

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Assignment (2) – Q14 (c) AC [Derive control inputs (LD, CLR, INR)]

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Assignment (2) – Q15

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Assignment (2) – Q16

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[Assignment 3 solution [Dr Mohamed Abd El Aziz + Dr Ahmed El Ghamdi

[Assignment 4 solution [Dr Mohamed Abd El Aziz + Dr Ahmed El Ghamdi

Final Exam Spring 2022, 42-43 احمد الغامدي

Final Exam 2023 Dr Ahmed El Ghamdi

Final Term Fall 2023, (44-45)H Dr Hesham بنات

Final Term Fall 2023, (44-45)H Dr Hesham ولاد

تقييمات ومراجعات الطلاب

لا يوجد تقييم حتى الآن

محتوى الدورة

Chapter 1 Register Transfer & Microoperation

تمرين مهم Midterm 2024 Exam Spring 2024 – (44-45H) Dr Hesham Question 2 (bus system using MUX and Decoder )

7. Microoperations

8. Arithmetic Circuit

9. Full Arithmetic Circuit

10. Logic Microoperations

11. Application of Logic Microoperations

12. Shift Microoperation

13. Hardware Implementation Shift Microoperation

14. Arithmetic Logic Shift Unit

chapter 1 تجميعات علي

quiz 1 solution حل

quiz 2 solution حل

quiz 3 solution حل

تحميل تجميعات MCQ علي شابتر 1 pdf

تجميعات علي شابتر 1 من الفاينال

Final Exam Spring 2022, 42-43 احمد الغامدي Question 1 – (a) [on chapter 1]

Final Exam Spring 2022, 42-43 احمد الغامدي Question 2 – (a) [on chapter 1]

Final Exam 2023 Dr Ahmed El Ghamdi [on chapter 1] Question 1.1

Final Exam 2023 Dr Ahmed El Ghamdi [on chapter 1] Question 1.2

Chapter 2 Basic Computer Organization and Design

2.1 Instruction Codes – a) The Basic Computer

2.1 Instruction Codes – b) Instruction Format and Addressing Modes

2.2 Computer Registers – a) Basic Computer Registers

2.2 Computer Registers – b) Basic Computer Common Bus System

2.3 Basic Computer instructions

2.4 Timing and Control

2-5 part 1 Instruction Cycle

2-5 part 2 Register Reference Instructions

2.6 Memory Reference instructions

2.7 Input-Output and Interrupt

2.8 Complete Computer Description

2.9 Design of Basic Computer

2.10 part 1 Design of Accumulator Logic

ملخص قوانين الشابتر pdf

chapter 2 تجميعات علي

quiz 1 solution حل

quiz 2 solution حل

quiz 3 solution حل

Chapter 3 Programming The Basic Computer

3.1 Introduction

3.2 Machine Language

3.3 (a) Assembly Language

3.3 (b) Pseudo-Instructions

3.3 (c) Translation to Binary

3.4 The Assembler

3.5 Programming Arithmetic and Logic Operations

ملخص قوانين الشابتر pdf

chapter 3 تجميعات علي

chapter 3 تجميعات علي

Midterm 2022 first term [Dr Ahmed AL-Ghamdi]

Midterm 2022 first term – Q1-(a)

Midterm 2022 first term – Q1-(b)

Midterm 2022 first term – Q1-(c)

Midterm 2022 first term – Q1-(d)

Midterm 2022 first term – Q2-(a)

Midterm 2022 first term – Q2-(b)

Midterm 2022 first term – Q3

Midterm 2022 second term [Dr Ahmed AL-Ghamdi]

Midterm 2022 (Q1) solution

[Problem 5.12 solution book ] Midterm 2022 (Q2) solution

Midterm 2022 (Q3) solution

Midterm 2024 Exam Spring 2024 – (44-45H) Dr Heham (الاختبار علي أول 3 شباتر)

Question 1 (MCQ)

Question 2 (bus system using MUX and Decoder )

Question 3 [Problem 5.12 solution book ]

Question 4 [Problem 6.1 solution book ]

Midterm Exam, Spring 2023, 44-45 Dr Hatem

Question 1 [Design an arithmetic circuit ]

Question 2 [An instruction at address 333 in the basic computer has I=1]

Question 4 [Analyze the bits in the Instruction Register of the Basic Computer]

Question 5 [Design the Bus System that has two groups of registers (Sender Registers and Receiver Registers). ]

Midterm 2025, second term 1446 H [Dr Mohamed Abdelaziz]

Question 1 (a)

Question 1 (b)

Question 1 (c)

Question 2 (a) DR [Derive control inputs (LD, CLR, INR)]

Question 2 (b)

Chapter 4 Central Processing Unit